Computer systems are well known in the art. In particular, a computer system adhering to the “IBM PC” standard is well known in the art. Referring to FIG. 1, there is shown a computer system 10 of the prior art. The computer system 10 conforms to the “IBM PC” architecture. The system 10 comprises typically a motherboard 12 on which are mounted a variety of components such as a processor 14, such as a Pentium microprocessor made by Intel Corporation, a memory controller hub (MCH) chip 16, and a IO controller hub (ICH) chip 18. The MCH 16 and the ICH 18 are known as chipsets and can be obtained from Intel Corporation. Finally, the motherboard 12 comprises a BIOS 20 which is typically a non-volatile memory device. The foregoing system is described and is disclosed in U.S. Pat. No. 6,421,765. See also U.S. Pat. No. 6,330,635.
Intel Corporation, a developer of the MCH chip 16, also developed the ICH chip 18 which has a particular feature known as a low pin count (LPC) bus. See, for example, U.S. Pat. No. 5,991,841. The LPC bus communicates between the ICH chip 18 and the BIOS 20. At the time that Intel Corporation introduced the LPC bus 30, it disclosed that the LPC bus 30 is operable in accordance with the standard as disclosed in FIG. 2. This is also disclosed in U.S. Pat. No. 5,911,841. The LPC bus 30 comprises four signal lines between the ICH chip 18 and the peripheral devices such as the BIOS memory device 20. Along the four signal lines, designated as LAD [3:0], are supplied command, data and address signals. As shown in FIG. 2, the initial field for the LAD bus is a start field. This is then followed by the address and the data signals.
Initially, when Intel Corporation opened or disclosed the format of the LPC bus 30, it disclosed to the public that the ICH chip 18 is operable with a memory device 20 only in accordance with the FWH protocol. Thus, Intel disclosed that when the LAD [3:0] signals had the bit pattern of “1101” or “1110” in the start field, then that represents communication with a BIOS memory device 20.
At the time that Intel announced the FWH protocol for the ICH chip 18, other semiconductor chip makers also made and sold chipsets, such as the combination of MCH chip 16 and ICH chip 18 that communicate in the LPC protocol. However, these chipset makers established a protocol in which the start field having the bit pattern of “0000” would mean the start of a cycle for the BIOS memory device 20. Thus, to a manufacturer and supplier of a BIOS memory device 20, the manufacturer must maintain two sets of inventory: one set of memory device 20 that is operable under the FWH protocol for Intel and another set of memory devices 20 that are operable with the LPC protocol from other chipset makers. It should be noted that the difference in operation between the LPC protocol and the FWH protocol is well known in the art. For example, the address field and select field are handled slightly differently in the LPC and FWH as well as the decoding of these. In the FWH protocol, there are four (4) bits of the IDSEL field and 28 bit address field. In the LPC protocol there are 32 bit address field with IDSEL included.
On Aug. 20, 2002, Intel announced that its ICH chip 18 would be able to operate with a BIOS memory device 20 with either the FWH protocol or the LPC protocol. For the manufacturer of the BIOS memory device 20, having a memory device which is operable in two protocols would eliminate the inventory problem.
Hence, this is one of the objectives of the present invention.